Design verification is the process of determining whether an integrated circuit, board, or system-level architecture, exactly implements the requirements defined by the specification of the architecture for that device. Design verification for a device under. testing (DUT) may be performed on the actual device, or on a simulation model of the device. For the purposes of explanation only and without intending to be limiting in any way, the following discussion centers upon testing which is performed on simulation models of the device.
As designs for different types of devices and device architectures become more complex, the likelihood of design errors increases. However, design verification also becomes more difficult and time consuming, as the simulation models of the design of the device also become more complex to prepare and to test.
The problem of design verification is compounded by the lack of widely generalizable tools which are useful for the verification and testing of a wide variety of devices and device architectures. Typical background art verification methods have often been restricted to a particular device having a specific design, such that the steps of preparing and implementing such verification methods for the simulation model must be performed for each new device.
The process of verifying a design through a simulation model of the device is aided by the availability of hardware description languages, or HDL, such as Verilog and VHDL. These languages are designed to describe hardware at higher levels of abstraction than gates or transistors. The resultant simulated model of the device can receive input stimuli in the form of test vectors, which are a string of binary digits applied to the input of a circuit. The simulated model then produces results, which are checked against the expected results for the particular design of the device. However, these languages are typically not designed for actual verification. Therefore, the verification engineer must write additional programming code in order to interface with the models described by these hardware description languages in order to perform design verification of the device. In particular, the e verification specific language is highly useful for design verification.
One example of a useful verification language is the e language which is provided by the Specman™ functional programming environment (Verisity Design, Inc., Mountain View, Calif., USA) and disclosed in U.S. Pat. No. 6,182,258, filed on Feb. 6, 1998, which is hereby incorporated by reference as if fully set forth herein. Although the e language is highly useful for creating programs for design verification, it still has certain drawbacks. For example, like most software languages, e code does not have a clear static structure, and the dynamic functionality of the model is open to interpretation at runtime, most notably with regard to timing. By contrast, hardware description languages have a more clear static structure and are less ambiguous with regard to issues such as timing. However, this latter type of language does not inherently provide the dynamic aspects of verification languages such as the e language.